Simulations also show that the proposed LUT functions properly even RRAM resistances deviates 20% from the design value. The maximal operating frequency reaches 1GHz at 10mV input difference. Compared to a 6-input SRAM-based LUT, the proposed RRAM-based one cuts off 60.4% of layout area. Furthermore, the expanded RRAM crossbar array together with the latch comparator based sense amplifier can dramatically reduce design complexity, decrease area cost, and improve tolerance on process variations. A new decoding scheme that supports dynamic programming is introduced. In this work, we propose a novel peripheral circuit for RRAM-based LUT. However, the complex peripheral circuit design to satisfy performance and accuracy requirements becomes a major issue. Eodem modo patet, circumferentiam circuli huius in omnibus 2m punctis, vbi U0, ab aliquo ramo lineae secundae secari. RRAM cells are fabricated at backend CMOS process and have negligible area cost. Resistive random access memory (RRAM) is a promising candidate to substitute static random access memory (SRAM) in lookup table (LUT) design for its high density and non-volatility. 2012 IEEE International Symposium on Circuits and Systems, 1811-1814. A novel peripheral circuit for RRAM-based LUT. USP1984014426764.A novel peripheral circuit for RRAM-based LUTД¬hen, Y.-C., Li, H., & Zhang, W. Semiconductor memory device with peripheral circuits.

Kosa Yasunobu (Kodaira JPX) Shimizu Shinji (Koganei JPX).

Semiconductor memory device having a floating gate with improved insulation film quality. Semiconductor memory device and method for manufacturing the same.

Ishii Takeaki (Ooita JPX) Maeda Satoshi (Ooita JPX).

Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer. (Houston TX) Lien Jih-chang (Houston TX) Bhatia Shyam (Houston TX).

Semiconductor device having contact between wiring layer and impurity region. Okumura Yoshinori (Hyogo JPX) Hachisuka Atsushi (Hyogo JPX).Semiconductor device having a contact hole. Ohno Yoshikazu,JPX Shinkawata Hiroki,JPX Yokoi Takahiro,JPX.SRAM with gate oxide films of varied thickness. Method of manufacturing semiconductor device provided with capacitor and resistor. Method of making semiconductor device with memory cells and peripheral transistors. Komori Kazuhiro (Kodaira JPX) Kuroda Kenichi (Tachikawa NY JPX) Sugiura June (Troy NY).Method of making random access memory device having memory cells each implemented by a stacked storage capacitor and a t. Method of making high performance capacitors and/or resistors for integrated circuits. Tung Yingsheng (Plano TX) Dixon Robert E.Method of making an integrated circuit comprising load resistors arranged on the field oxide zones which separate the ac. Winnerl Josef (Landshut DEX) Neppl Franz (Munich DEX).Method for fabricating semiconductor memory device. Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon. Lien Jih-Chang (Sugarland TX) Chiu Te-Long (Houston TX).

Field effect transistor having impurity regions of different depths and manufacturing method thereof. Arima Hideaki (Hyogo JPX) Ohi Makoto (Hyogo JPX) Ajika Natsuo (Hyogo JPX) Hachisuka Atsushi (Hyogo JPX) Okudaira Tomonori (Hyogo JPX).Dynamic random access memory having a reliable contact. Higasitani Masaaki (Kawasaki JPX) Shin Daitei (Kawasaki JPX) Nomura Toshio (Kawasaki JPX).A method of forming a transistor in a peripheral circuit of a dynamic random access memory device (DRAM), comprising the steps of:forming a first polysilicon layer over a substrate in an array region and in a peripheral region of the DRAM removing a portion of the first polysilicon layer in the array region to at least partially define a transistor gate in the array region after forming the transistor gate in the array region, forming a second polysilicon layer over the first polysilicon layer andpatterning the second polysilicon layer in the peripheral region and in the array region to form a periphery transistor gate in the peripheral region and a capacitor bottom electrode in the array region, the patterning performed through the use of a single mask step. A method of forming a transistor in a peripheral circuit of a dynamic random access memory device (DRAM), comprising the steps of:forming a first polysilicon layer over a substrate in an array region and in a peripheral region of the DRAM removing a portion of the first polysilicon layer in the array region to at least partially define a transistor gate in the array region after forming the transistor gate in the array region, forming a second polysilicon layer over the first polysilicon layer andpatterning the second polysilicon laye.

Peripheriam circuli